Samsung unveils a groundbreaking LPDDR5X-PIM memory chip that integrates processing within memory, dramatically boosting AI inference speeds in a compatible, cost-effective package suitable for mobile and edge devices, signalling a shift towards more accessible AI-enabled consumer hardware.
Samsung has taken a notable step towards making on-device artificial intelligence cheaper to run, showing working silicon of LPDDR5X-PIM at Hot Chips 2026. The chip is a form of low-power mobile DRAM that carries out some matrix operations inside memory rather than moving data back and forth to a processor. In Samsung’s demonstration, that approach lifted AI inference token throughput to 81.3 tokens per second from 27 tokens per second on conventional LPDDR5X, while keeping the same physical package and avoiding any need for a redesigned board. Tom’s Hardware said the result points to a practical route for bringing AI acceleration into devices that cannot easily accommodate the cost and complexity of high-bandwidth memory.
The technical case for the design is straightforward. During inference, models repeatedly fetch weights from memory, and that traffic can dominate both latency and power use. Samsung’s answer is to place processing-in-memory blocks across the chip’s 16 banks, each with scale and source register files and parallel multiply-accumulate trees. By keeping those calculations local, Samsung said effective bandwidth in PIM mode rises to 614 GB/s from 76.8 GB/s on the standard interface, an eightfold increase that comes from reducing movement, not widening the bus. Independent conference coverage from Tom’s Hardware and other outlets described the same architecture and bandwidth figures.
Samsung has also made compatibility a central part of the pitch. The LPDDR5X-PIM device uses the same 561-ball package as ordinary LPDDR5X and can work with a conventional memory controller, which means device makers would not need to redesign the printed circuit board to use it. Samsung’s Address Align Mode maps standard memory addresses to PIM operations, allowing the chip to switch between normal DRAM behaviour and in-memory computation when software requests it. That drop-in design matters because the company is aiming at smartphones, laptops and edge AI systems, where HBM-style packaging is often too expensive or too cumbersome.
The company positioned the chip as a complement to HBM rather than a replacement. HBM still offers far higher raw bandwidth and remains the better fit for large-scale training and cloud inference, but Samsung is targeting a different class of product: devices where cost, power draw and physical simplicity matter more than absolute throughput. Reports across Tom’s Hardware, SammyFans and 00011000 highlighted benchmark data from Meta’s Llama 3.1 8B model, which Samsung said was enough to show a 2.28-times reduction in task time, from 12.3 seconds to 5.4 seconds, alongside the throughput gain. Samsung also acknowledged that output accuracy still needs refinement, although it said the gap is being addressed.
The broader significance is that Samsung appears to have moved processing-in-memory from a research idea into working consumer silicon. The company has discussed LPDDR6-PIM standardisation with JEDEC, and that matters because an open specification would make the technology easier for other vendors to adopt and less risky for OEMs to design around. For now, however, LPDDR5X-PIM remains a first-mover product in a market that is still forming. If Samsung can translate the Hot Chips demonstration into shipping systems, it could create a new class of AI-capable memory for edge devices without forcing the industry to rebuild the platform around it.
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