Taiwan Semiconductor Manufacturing Company unveils A16, a revolutionary process integrating backside power rail technology to boost chip performance and density ahead of industry rivals, with volume production expected by late 2026.
TSMC has moved to strengthen its lead in the race towards angstrom-class manufacturing with A16, a process designed for chips that need both high performance and dense power delivery. According to TSMC’s own technology pages, the node combines nanosheet transistors with a backside power rail system called Super Power Rail, a layout intended to free up front-side routing for signals and reduce IR drop.
The company says A16 is more than a simple shrink. By shifting power delivery to the back of the wafer, TSMC claims it can keep gate density, footprint and device-width flexibility close to its N2P design rules while improving efficiency. The company’s published specifications say A16 should deliver 8% to 10% more speed at the same voltage, or cut power use by 15% to 20% at the same speed, while lifting chip density by up to 10%.
That positioning matters because TSMC has already begun volume production of its 2-nanometre N2 process, and N2P is described by the company as a further refinement with higher performance and better density. A16 is aimed at customers building AI and high-performance computing chips, where dense power networks and complex signal routing make traditional front-side power delivery increasingly difficult.
The backdrop is a broader industry push to move power delivery behind the transistor layer. Intel was first to publicise backside power delivery with PowerVia, but reports cited by the Chinese-language press suggest its approach required more changes to cell architecture. Samsung is also developing a similar technique for its SF2 node. Tom’s Hardware reported that TSMC’s updated roadmap now points to later angstrom-era nodes beyond A16, although the company’s public materials still describe A16 as production-ready in the second half of 2026.
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