Taiwan Semiconductor Manufacturing Company (TSMC) has revealed significant reductions in cost and development time for AI processors through chiplet-based 3DIC designs, signalling a disruptive shift in AI silicon manufacturing.
TSMC has put hard numbers on why chiplet-based AI processors have become the industry default. At the Open Compute Project APAC Summit in Taipei on 11 August, the company’s advanced packaging and services vice-president, Ho Jun, said a 3DIC design built around chiplets can cut total ownership cost by 22% and reduce the development cycle from two years to one. The presentation gave a rare quantitative view of how advanced packaging is changing the economics of AI silicon.
The shift away from monolithic system-on-chip designs is being driven by scale as much as by performance. As AI models grow larger, single-die processors become harder to manufacture efficiently because bigger dies tend to suffer lower yields and require a full redesign each time a process node changes. Chiplets split a processor into smaller functional blocks, allowing compute dies to use leading-edge manufacturing while less demanding input-output functions remain on mature nodes. That lets designers balance performance, yield and cost more effectively.
TSMC’s cost model shows that the savings do not come from cheaper packaging. In the company’s example, a chiplet design moved the die-cost index from 1.0 to 0.76, a 24% reduction, while packaging and assembly costs rose by around 2%. The net result was a 22% reduction in total cost. The key saving is therefore in the silicon itself, not in the packaging step. The model also assumes bin pairing, in which better-performing dies are matched together to improve overall package performance. TSMC stressed that the figure is illustrative rather than universal, and actual savings will vary by design and yield.
Speed to market is another reason chiplets are winning favour. Ho said next-generation 3DIC programmes once took around two years from development to volume production. By pushing system and technology co-optimisation earlier into the design flow, TSMC says that period can now be compressed to roughly one year, bringing mass production forward by about nine months. That matters in the race to supply cloud providers building out new AI infrastructure.
The presentation also clarified how TSMC’s two best-known advanced packaging platforms fit together. CoWoS is a 2.5D approach used to combine compute dies with high-bandwidth memory, while SoIC is a 3D stacking technology that uses hybrid bonding to place chips directly on top of one another. TSMC said SoIC can deliver about 56 times the interconnect density and roughly five times the energy efficiency of CoWoS. In practice, the technologies are complementary: SoIC can be used to stack logic dies, then CoWoS can connect the package to HBM.
Ho also highlighted a less visible issue: system reliability. He argued that the main challenge for future AI racks is no longer just the chip, but the full system. If an AI cabinet is expected to meet consumer-grade reliability of about 1,000 DPPM, each packaging layer must fall below roughly 12 DPPM. He said component-level testing is no longer enough because thermal stress can alter behaviour once parts are installed in a system. A package that looks sound in one stage can fail later, while one with minor cracks may behave differently after integration.
For Taiwan’s supply chain, the message is both opportunity and pressure. Ho said demand from AI has tightened supply of glass cloth used in substrates, and sourcing has expanded from a highly concentrated base to more than five suppliers. But every new material source brings differences in thermal expansion and other properties, which can affect flatness, yield and package reliability. In other words, material substitution is no longer just a procurement decision; it is a verification challenge that raises the technical bar for substrate, carrier and materials suppliers.
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