Samsung says customer-specific designs in processing-in-memory and 3D-stacked HBM are making common standards harder to establish, even as LPDDR5X-PIM performance improves.
Samsung Electronics has drawn attention to the difficulty of turning next-generation AI memory into shared industry standards, saying the move from conventional DRAM towards designs that combine storage and compute is making customisation far more complex. At the JEDEC Forum in Seoul on 15 October, held alongside SEDEX 2026 at COEX, Samsung researcher Hwang Ga-ram said LPDDR-based processing-in-memory and z-high-bandwidth memory contain many customer-specific features that are hard for manufacturers to handle in volume production. According to Samsung, this problem is not unique to its own roadmap and is likely to confront other memory makers as well.
The issue matters because standards have traditionally provided the common rules that let memory chips from different suppliers work to the same specification. That model has been far easier to maintain with conventional DRAM than with newer architectures that embed processing inside the memory itself. LPDDR-PIM is one example: it places compute functions directly into low-power DRAM to cut the amount of data that must move back and forth between memory and processor. Hwang said Samsung hoped the LPDDR6-PIM standard could be agreed by the end of this year.
Samsung’s zHBM concept is even further from today’s mainstream packaging. Rather than the usual 2.5D arrangement, in which a processor and HBM sit side by side on an interposer, zHBM uses a 3D-stacked structure that connects HBM directly to the computing processor. The company says through-silicon vias are spread across the DRAM core dies to shorten data paths, which means the customisation reaches beyond the base die and into the wider structure of the memory itself. Hwang said not every function could be fully standardised, but added that JEDEC members should still try to define common ground where possible.
Samsung also used the forum to present updated performance figures for LPDDR5X-PIM. The company said bandwidth is eight times higher than that of conventional LPDDR5X, while AI inference performance reached 102 tokens per second, compared with 27 tokens per second for standard LPDDR5X. That is about 23% better than the 83 tokens per second Samsung showed at Hot Chips in August. Average power use rose to 11.5 watts from 8.4 watts, but Samsung said inference performance per watt improved to 9 tokens per second per watt, roughly 2.8 times the result of conventional LPDDR5X.
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